2 Bit Magnitude Comparator Logic Diagram
If input a 0 logic low then both gates are at zero potential pmos is on provide low impedance path.
2 bit magnitude comparator logic diagram. Logic diagram of 2 bit magnitude comparator 3. The logic circuit of a 2 bit comparator how to design a 4 bit comparator. By using above obtained boolean equation for each output the logic diagram can be implemented by using four not gates seven and gates two or gates and two ex nor gates. 2 bit magnitude comparator a comparator used to compare two binary numbers each of two bits is called a 2 bit magnitude comparator.
The truth table for a 2 bit comparator is given below. Using cmos logic style fig 3 a represents symbol of cmos inverter. Experiment 5 the 2 bit magnitude comparator a 2 bit magnitude comparator compares two 2 bit numbers. It consists of four inputs and three outputs to generate less than equal to and greater than between two binary numbers.
It is also possible to construct this comparator by cascading of two 1 bit comparators. The truth table for a 4 bit comparator would have 4 4 256 rows. So we will do things a bit differently here. The figure below shows the logic diagram of a 2 bit comparator using basic logic gates.
2 bit magnitude comparator design using different logic styles 3 1. A b f a b f a b f a b. 2 bit comparator similarly we can have 2 bit comparator and the table to list all the combinations at input and their corresponding outputs is as. Magnitude comparator a magnitude comparator is a digital comparator which has three output terminals one each for equality a b greater than a b and less than a b.
Gate 1 produces the function a b and gate 3 gives a b while gate 2 is an xnor gate giving an equality output. A simple 1 bit magnitude comparator is shown in fig 4 3 2. The purpose of a digital comparator is to compare a set of variables or unknown numbers for example a a1 a2 a3. From the truth table you realize immediately that a 2 bit magnitude comparator is much more demanding.